The present invention relates to designing of a semiconductor integrated circuit, and more particularly, to a method for correcting a timing error when designing a semiconductor integrated circuit with a hierarchical design technique.
FIG. 1 shows an example of a data transfer circuit designed with a hierarchical design technique. In FIG. 1, layout blocks 1a and 1b are designed beforehand for a layer lower than the data transfer circuit.
The uppermost hierarchical layer in the data transfer circuit includes the two layout blocks 1a and 1b, four flip flop circuits FF1 to FF4, and six cells c1 to c6. The layout block 1a includes three single-input cells c7 to c9, a multiple-input cell c10, and four flip flop circuits FF01 to FF04. The layout block 1b includes three single-input cells c11 to c13, a multiple-input cell c14, and four flip flop circuits FF05 to FF08.
The flip flop circuits FF1 to FF4 and FF01 to FF08 each input and output data in accordance with a clock signal. In FIG. 1, the clock signal is not shown.
The data provided from the flip flop circuit FF1 is sent via the cells c3, c2, c7, and c9 to the flip flop circuits FF02 and FF03 and via the cells c3, c2, c7, c8, and c10 to the flip flop circuit FF01. The data provided from the flip flop circuit FF3 is sent via the cell c1 to the flip flop circuit FF04 and via the cells c1 and c10 to the flip flop circuit FF01.
The data provided from the flip flop circuit FF4 is sent via the cells c4, c5, and c6 to the flip flop circuit FF08 and via the cells c4, c5, c6, and c14 to the flip flop circuit FF05. The data provided from the flip flop circuit FF2 is sent via the cells c11, c12, and c14 to the flip flop circuit FF05 and via the cells c11 and c13 to the flip flop circuits FF06 and FF07.
The numbers marked at opposite ends of the cells c1 to c14 and the numbers marked at the input ends of the flip flop circuits FF01 to FF08 each indicate a delay margin time Slack until a set up timing error occurs in the cells c1 to c14 and the flip flop circuits FF01 to FF08. The unit of the delay margin time Slack is ps. Further, the delay margin time Slack of each of the multiple-input cells c10 and c14 is set in accordance with the delay margin time Slack of the input pin that is under a harsher condition.
FIG. 2 shows the hold time and the setup time of a flip flop circuit. In the flip flop circuit FF shown in FIG. 2(a), when data DATA is retrieved in response to the rising edge of the clock signal CLK, a setup time ST that is longer than or equal to a predetermined time must be provided from when the data DATA that is to be retrieved is input to when the clock signal goes high, as shown in FIG. 2(c). Further, a hold time HT that is longer than or equal to a predetermined time must be provided from when the clock signal CLK goes high to when the input of the data DATA that is to be retrieved ends, as shown in FIG. 2(c). A setup timing error occurs when the setup time ST cannot be provided, and a hold timing error occurs when the hold time HT cannot be provided.
For example, in pass A extending from the flip flop circuit FF3 to the flip flop circuit FF01, when a hold error occurs in the flip flop circuit FF01, the adjustment time, or the data delay time required to correct the hold error is 45 ps. In pass B extending from the flip flop circuit FF1 to the flip flop circuit FF01, when a hold error occurs in the flip flop circuit FF01, the adjustment time, or the data delay time required to correct the hold error is 140 ps. In pass C extending from the flip flop circuit FF2 to the flip flop circuit FF06, when a hold error occurs in the flip flop circuit FF06, the adjustment time, or the data delay time required to correct the hold error is 120 ps.
Japanese Laid-Open Patent Publication Nos. 2003-162556, 2003-256488, and 2000-250963 each describe a method for correcting a hold error such as that described-above.